1. Field
Example embodiments relate to a high voltage generating circuit and/or a semiconductor memory device having the same and/or a method thereof.
2. Description of Related Art
In conventional semiconductor memory devices, e.g., Dynamic Random Access Memory (DRAM), an NMOS transistor is used as a switching element of a memory cell. Accordingly, a voltage that is applied to a gate terminal of the NMOS transistor of the selected memory cell needs to be higher than a voltage level of data stored or to be stored in the memory cell by the threshold voltage of the NMOS transistor. Therefore, the DRAM includes a high voltage generating circuit that generates a high voltage Vpp larger than a power supply voltage supplied from the outside.
High voltage generating circuits may be included to correspond to individual memory banks. During a normal operation of the DRAM, only the high voltage generating circuits corresponding to the selected memory banks are enabled to output the high voltage Vpp, and the high voltage generating circuits corresponding to the unselected memory banks are disabled to not output the high voltage Vpp. During an automatic refresh (or a column address strobe (CAS) before row address strobe (RAS) refresh (hereinafter, referred to as a “CBR refresh”)) operation, all the high voltage generating circuits are enabled together to output the high voltage Vpp.
Accordingly, a fluctuation in the high voltage Vpp is increased, and excessive stress is applied to the memory cells.